Field of the Invention
This invention relates to digital-to-analog converters (DACs) and more particularly to use of a DAC to reduce quantization error in a phase-locked loops (PLL).
Description of the Related Art
FIG. 1 illustrates a prior art analog fractional-N PLL where the VCOCLK 101 is a non-integer multiple of the reference clock (REFCLK) 103. The fractional-N divider 107 supplies a feedback signal (DIVOUT) 108 to a phase and frequency detector (PFD) and charge pump 110 that determines the time difference between edges of the REFCLK signal 103 and the feedback signal 108 and supplies a phase error signal based on the time difference to the loop filter 119. The divide value 105, which is supplied to the fractional-N divider 107, is modulated in time to achieve an average divide value corresponding to the desired divide value 109 supplied to the delta sigma (Δ−Σ) modulator logic 111. The delta sigma modulator logic 111 supplies a digital error signal 115 based on the difference between the divide value 105 supplied to the fractional-N divider and the desired divide value 109. The illustrated prior art PLL includes a digital-to-analog converter (DAC) 117 having a current-based output to convert the digital error signal 115 to a current that is added to the charge pump output signal and supplied to the loop filter 119 to reduce quantization noise.
While FIG. 1 shows an analog PLL, digitally controlled oscillators have become common in PLLs. There is a need to achieve high resolution conversion of the phase error between the feedback clock and the reference clock to a digital value. Accordingly, improvements in generating a digital representation of the phase error are desirable.